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uniwill_wmi: Tweak debug cycle view threshold
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parent
9a3504750f
commit
57455cfb9f
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@ -177,7 +177,7 @@ static int uw_ec_read_addr_direct(u8 addr_low, u8 addr_high, union uw_ec_read_re
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if (bflag)
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if (bflag)
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pr_debug("addr: 0x%02x%02x value: %0#4x result: %d\n", addr_high, addr_low, output->bytes.data_low, result);
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pr_debug("addr: 0x%02x%02x value: %0#4x result: %d\n", addr_high, addr_low, output->bytes.data_low, result);
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if ((UW_EC_BUSY_WAIT_CYCLES - count) >= 1)
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if ((UW_EC_BUSY_WAIT_CYCLES - count) > 1)
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pr_debug("read wait count: %i", (UW_EC_BUSY_WAIT_CYCLES - count));
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pr_debug("read wait count: %i", (UW_EC_BUSY_WAIT_CYCLES - count));
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// pr_debug("addr: 0x%02x%02x value: %0#4x result: %d\n", addr_high, addr_low, output->bytes.data_low, result);
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// pr_debug("addr: 0x%02x%02x value: %0#4x result: %d\n", addr_high, addr_low, output->bytes.data_low, result);
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@ -241,7 +241,7 @@ static int uw_ec_write_addr_direct(u8 addr_low, u8 addr_high, u8 data_low, u8 da
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if (bflag)
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if (bflag)
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pr_debug("addr: 0x%02x%02x value: %0#4x result: %d\n", addr_high, addr_low, data_low, result);
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pr_debug("addr: 0x%02x%02x value: %0#4x result: %d\n", addr_high, addr_low, data_low, result);
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if ((UW_EC_BUSY_WAIT_CYCLES - count) >= 1)
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if ((UW_EC_BUSY_WAIT_CYCLES - count) > 1)
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pr_debug("write wait count: %i", (UW_EC_BUSY_WAIT_CYCLES - count));
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pr_debug("write wait count: %i", (UW_EC_BUSY_WAIT_CYCLES - count));
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mutex_unlock(&uniwill_ec_lock);
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mutex_unlock(&uniwill_ec_lock);
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